The present invention relates generally to computing systems, and more specifically, to cross-pipe serialization for a multi-pipeline computer processor.
A processor in a computing system may include a pipeline having a plurality of pipeline stages. This enables multiple instructions to be in the process of execution by the processor at any point in time. During the execution of any particular instruction, that instruction will pass sequentially through the various pipeline stages of the processor. Execution of that instruction may complete when the instruction is processed through the final pipeline stage of the main processor.
A processor in a computing system may additionally include multiple pipelines. In a multi-pipeline computing system, resources may be shared by requests from multiple pipelines. Starvation or lock-out scenarios may occur if access to these resources is not arbitrated fairly between requests. Even if all requestors are eventually given access to a shared resource, system performance may be negatively affected if an unequal preference is unintentionally given to one request or group or requests. A pipeline arbitration system may be used to provide fair access to a shared resource in a multi-pipeline processor system. However, resonant frequency lockouts may result, due to rank or simplified pipe request algorithms. Resource arbitration is additionally complicated in a multi-pipeline processor system in which high-level requests generate multiple subrequests that are serviced by more than one pipeline. In a system with a relatively large number of requestors, resource arbitration algorithms such as a least recently used (LRU) scheme may only handle prioritization within the same pipeline instance, and may not ensure fairness between requests that span multiple pipelines.